1. Field of the Invention
The invention relates to the processing of design data and, in particular to placing phase shifting regions and assigning phase to such regions for different formats of design data.
2. Description of the Related Art
Lithography is a well-known process used in the semiconductor industry to form lines, contacts, and other known structures in integrated circuits (ICs). In conventional lithography, a mask (wherein the term “mask” as used herein can refer to a mask or a reticle) having a pattern of transparent and opaque regions representing such structures in one IC layer is illuminated. The emanating light from the mask is then focused onto a photoresist layer provided on a wafer. During a subsequent development process, portions of the photoresist layer are removed, wherein the portions are defined by the pattern. In this manner, the pattern of the mask is transferred to (i.e. printed on) the photoresist layer.
However, diffraction effects at the transition of the transparent regions to the opaque regions on the mask can render the corresponding printed edges on the wafer indistinct, thereby adversely affecting the resolution of the lithography process. Various techniques have been proposed to improve the resolution. One such technique, phase shifting, uses phase destructive interference of the waves of incident light. Specifically, phase shifting shifts the phase of a first region of incident light waves approximately 180 degrees relative to a second, adjacent region of incident light waves to create a sub-wavelength feature between the first and second regions. Thus, a feature, as defined by exposed and unexposed portions of a photoresist illuminated through a mask, can be more closely defined by using phase shifting, thereby allowing greater structure density on the IC. As the need for feature density increases, phase shifting is being applied to many features in the design data (which defines the pattern of transparent and opaque regions for the mask).
There are two common formats for design data: flattened and hierarchical. Each format has advantages and disadvantages. For example, flattened design data, e.g. layouts, are geometrical in nature and therefore adjacency between structures can easily be determined. However, flattened design data can result in an extremely large file size, e.g. 10-15 GB, for a layer. In contrast, hierarchical design data are more space efficient because multiple copies of a single geometry can be stored once and then referenced in other locations. Unfortunately, hierarchical design data are not well suited for performing geometrical operations because adjacency and position information must be computed.
The positioning of phase shifting regions (hereinafter shifters) and the assignment of phase to such shifters is a highly geometrical operation. Therefore, a need arises for a system and method of efficiently processing design data for one or both formats.